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Senior EDA Back-end Software Engineer ×ÊÉîEDAºó¶ËÈí¼þ¹¤³Ìʦ | [²é¿´¸ü¶àÀàËÆÖ°Î»] |
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ְλÀà±ð£º ¼ÆËã»úÈí¡¢Ó²¼þ/»¥ÁªÍø/IT ¹¤×÷µØµã£º ±±¾© ·¢²¼ÈÕÆÚ£º 2008-05-20 ¹¤×÷¾Ñ飺 3-5Äê ×îµÍѧÀú£º ²»ÏÞ ¹ÜÀí¾Ñ飺 ·ñ ¹¤×÷ÐÔÖÊ£º ȫְ ÕÐÆ¸ÈËÊý£º 2ÈË Ö°Î»ÃèÊö/ÒªÇó£º Job Responsibilities: Independently specify, design, implement and test software components as part of a modern state-of-the-art EDA design tool chain supporting our configurable system-on-chip solutions. Requirements: Ph.D., M.S. with at least 3 years of experiences, or B.S. with 5 years of experiences in related areas; At least 2 plus years of experiences in EDA software development with solid understanding in at least one area of EDA algorithms; Excellent strong programming skills in object-oriented design, C++; Good team player with communication and management skills. Preferences: Knowledge of algorithms used in RTL/logic synthesis, technology mapping, placement, routing, timing models and analysis, and/or FPGA architectures. Familiar with shell scripts, Python, Perl and/or Tcl. ְλְÔ𣺠¶ÀÁ¢µØÍê³É EDA Éè¼Æ¹¤¾ßµÄÃèÊö¡¢Éè¼Æ¡¢ÊµÏÖÓë²âÊÔµÈÏà¹Ø¹¤×÷£¬ÌṩÍêÕûµÄ¿ÉÅäÖÃÆ¬ÉÏϵͳ½â¾ö·½°¸¡£ ְλҪÇó£º ´óѧ˶ʿÒÔÉÏѧÀú£¬ÈýÄêÏà¹Ø¹¤×÷¾Ñ飻»òÕß±¾¿ÆÑ§Àú£¬ÓÐ 5 ÄêÏà¹Ø¹¤×÷¾Ñé ÖÁÉÙÓÐ 2 ÄêÒÔÉÏ EDA Èí¼þ¿ª·¢¾Ñ飬 C++ ±à³ÌÄÜÁ¦Ç¿ ÓÐÍŶӾ«Éñ£¬ÓïÑÔ¹µÍ¨ÄÜÁ¦Ç¿£¬ÓÐÒ»¶¨¹ÜÀíÄÜÁ¦ Á˽â RTL/Logic ×ۺϣ¬¼¼ÊõÓ³É䣬²¼¾Ö²¼Ïߣ¬Ê±Ðò·ÖÎö¼° FPGA ¼Ü¹¹ÕßÓÅÏÈ ÁªÏµ·½Ê½£º µØÖ·£º±±¾©º£µíÇøÇ廪¿Æ¼¼Ô°´´Òµ´óÏà Email: hr@agatelogic.com.cn Çë×¢Ã÷ÄúËùÒªÉêÇëµÄְλÃû³Æ¡£ Çë×¢Ã÷ÄúµÄ»§¿ÚËùÔڵء£ ÇëÄúÔÚӦƸ²ÄÁÏÉϱêÃ÷£¬´ËְλµÄÐÅÏ¢À´Ô´ÓÚzhaopin.com. .
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