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  威盛电子(中国)有限公司

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Logic Verification Engineer

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工作地点
 北京
发布日期
 2008-05-17
工作年限
不限
薪水范围
面议
学历要求
硕士  
职位描述
职位类别: 在校学生 工作地点: 北京 发布日期: 2008-05-15 工作经验: 不限 最低学历: 硕士 管理经验: 否 工作性质: 实习 招聘人数: 6人 职位描述/要求: 【 Responsibilities 】 Logic design verification 【 Requirements 】 1. M.S/B.S in Computer Science or Electrical Engineering; 2. Digital design or verification experience in IC or FPGA; 3. Available for at least six months and four days a week; 4. Graduate students who will graduate in 2009 are preferred. 联系方式: 简历接收信箱: hrbj_3@viatech.com.cn .
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