职位类别： 电子/半导体/仪表仪器 工作地点： 北京 发布日期： 2008-03-20 工作经验： 5-10年 最低学历： 本科 管理经验： 否 工作性质： 全职 招聘人数： 若干 职位月薪： 1000-50000元/月 职位描述/要求： Job Responsibilities: Synopsys seeks an experienced digital design manager with strong customer and communication skills, to build and lead a team that will provide integration services and support for design teams using DesignWare IP. The successful candidate will: *Recruit, hire, train, and manage a team of engineers to provide IP integration services and support. *Build technical expertise in key interface protocols used in many SoC designs including: USB, PCIe, DDR3/DDR2, Ethernet, WUSB as well as in all design methodologies (verification, synthesis, test, power optimization, etc.) necessary to implement these protocols in an SoC using DesignWare IP. *Be highly visible as the local representative of the Synopsys IP R organization. *Work closely with customers to make their projects successful and to become a key participant in their chip designs. Job Requirements: *MSEE with 5+ years of experience or BSEE with 7+ years of experience.*Proven track record managing ASIC design teams.*Strong customer, communication, and program management skills.*Good knowledge of all aspects of front-end design: Verilog design, verification, synthesis, timing analysis, test, and power optimization.*Knowledge of one or more of the following protocols a strong plus: USB, WUSB, PCIe, DDR3/DDR2, SATA, Ethernet. 联系方式： Contact : Synopsys recruiter Email : jobs-china@synopsys.com .
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