职位类别： 电子/半导体/仪表仪器 计算机软、硬件/互联网/IT 工作地点： 上海 发布日期： 2008-02-19 工作经验： 3-5年 最低学历： 本科 管理经验： 否 工作性质： 全职 招聘人数： 1人 职位描述/要求： Job Description -Development of the cutting edge communication and consumer ASICs. Responsibilities include all phases of ASIC front-end design, development, and documentation tasks include concept development, requirements, verification plan, chip architecture, detail RTL design, simulation, timing analysis, synthesis, etc. Job Requirement -BSEE required and MSEE preferred plus 3 years of directly related ASIC/FPGA design experience -Expertise in logic block designs, Verilog/VHDL RTL coding, synthesis and static timing analysis -Experience creating self-checking test benches, simulations, and perform laboratory debugging -Experience in SoC designs is a great plus -Working knowledge of telecommunication is a plus -Experience in ASIC back-end tasks such as fab supporting, DFT, Place and Layout is a plus -Must be self-motivated and work well in a team environment and under tight deadlines 联系方式： Email: cig_hr@ci-g.com Address: Building 4, 3/F, Block D,889,Yishan Rd., Shanghai 200233,China .
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