职位类别： 计算机软、硬件/互联网/IT 工作地点： 深圳 发布日期： 2008-01-30 工作经验： 3-5年 最低学历： 本科 管理经验： 否 工作性质： 全职 招聘人数： 1人 职位月薪： 10000-50000元/月 职位描述/要求： Position Details: - Supports current telecommunications products in manufacturing by providing component substitution specification and FA, RMA support as well as cost reduction activities. - Contribute to the transfer of new products to Asian manufacturing sites and subsequent cost reductions. - Interact with North American design teams to provide input for next generation telecommunications module designs. Inputs include design, circuit simulation, component selection, schematic entry, working closely with PCB layout, and testing/verification support. - Use previous experience (network analyzers, spectrum analyzers, TDR, BERT, scopes, etc) to verify new and existing designs. - Utilize, debug and eventually architect functional test stations - Contribute to DFMEA and PFMEA in the design phase. - The candidate must be an experienced digital HW designer with expertise in solving complex problems in high speed telecommunications modules and circuit packs. Required Qualifications: - 3+ Years of digital HW design, integration, test and documentation. - Experience developing HW for optical communications modules or instrumentation would be a definite asset. - Experience with Processors and FPGA’s using VHDL and Verlog designs using a variety of General knowledge across several disciplines including embedded SW/DSP, Digital, and Mechanical layout, and optical component testing. - Able to work with CAD tools such as Cadence tool set (electrical) and Solid Edge or similar, (Mechanical). - Experience with in-circuit test procedures, e.g. Boundary-scan. - Demonstrated ability to develop functional test procedures into a lower level test set instructions. - Good lab skills and knowledge of debug procedures. - Familiar with I2C bus and similar interfaces. - Fluent in English is a must. 联系方式： JDS Uniphase Shenzhen Limited 捷迪讯光电（深圳）有限公司 E-mail: hr.sz@jdsu.com 深圳市福田保税区红棉道 3 号 Http:// www.jdsu.com 518038 .
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