职位描述/要求： Specification, architecture definition, implementation, verification and synthesis；test plan creation； test bench development；self checking script generation；behavioral verification. Familiar with ModelSim (or other simulators), Quartus II. You will also be responsible for synthesis, static timing analysis and functional test vector generation. Requirements: At least 3 years experience in ASIC/FPGA Design in video compression Experienced Xilinx or Altera FPGA is a big plus MPEG, H.263, H.264 and other video compression and decompression techniques Digital Signal Processing and filter design Familiar with all stages in the ASIC and FPGA design flow including simulation, emulation, prototyping, programming skills in Verilog and C. Working experience and knowledge of embedded systems Must be highly motivated and skillful at solving difficult technical problems BSEE required, MSEE or Ph.D preferred .
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